The SIT3808 is a differential VCXO with 0.5 ps typical RMS phase jitter and 0.1% typical tuning linearity. It addresses the PLL and clock-recovery pain points of quartz VCXOs: inconsistent Kv, jitter margin and custom-frequency lead time.

YQM supplies authentic SITIME SIT3808 parts with datasheets, samples and FAE support for production programs.

Application Pain Points & Solutions

Pain: Quartz VCXO tuning slope (Kv) varies with control voltage, making PLL bandwidth and stability margin inconsistent
Solution: 0.1% typ / 1% max nonlinearity and consistent Kv simplify PLL and clock-synchronization design.
Pain: Clock jitter eats timing margin in high-speed links and sampling
Solution: 0.5 ps typ / 1 ps max RMS phase jitter (12 kHz–20 MHz; SIT3808 tested at 20 MHz) improves eye margin and reduces BER.
Pain: Multiple frequencies, voltages and pull ranges; non-standard frequencies mean sample wait and redesign
Solution: Combined 1–220 MHz coverage, ±25 to ±1600 ppm pull range, multiple supply/package options and field-programmable samples.
Pain: Legacy quartz footprint and control-voltage compatibility
Solution: 100% compatible with legacy quartz VCXO footprint and control voltage — drop-in without redesign.

Core Advantages

0.1% typ tuning linearity: Consistent Kv simplifies PLL loop design.
0.5 ps typ RMS jitter: Clean clock for SerDes, FPGA and audio/video links.
1–220 MHz / ±1600 ppm: Wide frequency and pull-range coverage.
Field-programmable: Fast samples for non-standard frequencies.

Specifications

Parameter	Value
Frequency	1 to 80 MHz
Frequency Stability (ppm)	±25, ±50
Operating Temperature Range (°C)	-20 to +70, -40 to +85
Package Type (mm²)	2.7x2.4, 3.2x2.5, 5.0x3.2, 7.0x5.0
Oscillator Type	VCXO-SE
Phase Jitter (rms)	0.5 ps
Pull Range (ppm)	±25, ±50, ±80, ±100, ±150, ±200
FlexEdgeTM Rise/Fall Time	Yes
Voltage Supply (V)	1.8, 2.5, 2.8, 3.3
Features	Low Jitter, Field Programmable

Original specification table (English).